The present invention relates to electric drives and, more particularly, to connected variable speed electric drives, which are controlled through frequency inverters with a common network feed.
In electrical drive systems, e.g. servo-drive systems, where several drives cooperate to produce a common coordinated movement, the control time slices of all drives are usually synchronized, i.e., they start in all drives at the same time. This is necessary so that the actual values (or each actual value) of all drives are determined at the same time and that corresponding adjusting commands are transmitted and implemented at the same time. This time slice synchronization involves all automatic control loops, from the position controller to the current controller.
To achieve the highest possible dynamics, a defined, constant dead time and an alias-free determination of the actual current value, the current control frequency and the duration of the control pulse of the converter are almost always synchronized in a variable speed drive, i.e. switching frequency and sampling rate are identical or have an integer ratio. The German published patent application DE 19723956 A1 describes an exemplary digital multi-axis control for controlling real time processes. Several decentralized drive instances are synchronized on a central control instance, whereby required system states and actual values can be stored at synchronous and equidistant times in a timing pattern of the corresponding instance, so that the assigned system states and measured values can be independently accessed at any time. Typically, the only exception from this rule are converters with a very low switching frequency and/or control processes with optimized pulse patterns, which however are not commonly used in servo applications.
FIG. 1 shows this relationship for two exemplary conventional drives with a converter sampling rate of 16 kHz and a switching frequency of 4 kHz. The control set utilizes a sinusoidal/triangular modulation. The upper portion of FIG. 1 shows the current controller clock ti1, an exemplary curve tp1 of the desired value of a phase voltage as well as the associated modulation triangle tm1 for the first drive as a function of time. The lower portion of FIG. 1 shows the same quantities ti2, tm2 and tp2 for the second drive.
In order to match the reaction rate of all drives as best as possible, the triangles of all drives in the system are synchronized, i.e. overlap temporally. The bottom portion of FIG. 1 shows the time dependence of the potentials of two inverter phases, drive 1 and drive 2, which essentially overlap and oscillate between half the positive and half the negative intermediate circuit voltage +Uzk/2 and −Uzk/2.
In control processes operating with space-division modulation, this corresponds to the synchronization of the modulation intervals (see FIG. 4 below).
When drives are connected in a servo system via frequency converters, all drives usually have a common intermediate circuit and a common power line feed. A line filter can also be part of the power line feed. The line filter typically includes a current-compensated choke, which can be quite expensive. In a current-compensated choke, the three windings of the three strands are wound with the same winding sense around a leg of the choke such that the corresponding fluxes cancel each other, when the sum of the currents is equal to zero. The choke represents high impedance for asymmetric currents, where the sum of the currents not equal to zero.
FIG. 2 shows the emergence of asymmetric interference currents in such systems and the effect of the line filter. A power line 1 supplies a three-phase voltage to an input stage 3 through a line filter 2. The input stage 3 is connected with an inverter 5 (WR) via an intermediate voltage circuit 4. Each phase is connected between the line filter 2 and the input stage 3 via a capacitor to ground potential. A motor 7 is connected to the inverter via an motor line 6. The motor 7 and the converters are grounded. Both the motor line 6 and the motor 7 have parasitic capacitances 9 to ground. The power line 1 and converters have parasitic impedances 9.
The triggering event is in each case a switching process in an inverter. For example, when an inverter phase makes a transition from a negative intermediate circuit potential to positive intermediate circuit potential, the charge of the parasitic capacitances 8 to ground in the cable 6 and in the motor 7 is reversed. A portion of the charge exchange current flows back via the cable shield to the converter, another portion returns via ground into the power line 1 and via the power line terminal to the converter.
The latter current path causes voltage drops across the impedances of the power line. These interference voltages can cause instabilities at other users. The current-compensated choke is intended to block the charge exchange currents flowing through the power line. The existing charge exchange currents then essentially return to the converter only via the ground connection of the converter, and hence do no longer produce interference voltages.
The magnetic part of the choke is sized according to the amplitude of the produced asymmetric interference currents. If the interference current becomes too large, the choke saturates, causing the electromagnetic interference to increase drastically.
The interference current of an inverter WR is particularly large, if the degree of modulation is very small, because the three inverter phases have the same direction and change the potential almost simultaneously, thus producing charge exchange currents with the same polarity. This situation arises with servo drives near a rotation speed of zero, which reflects an operating condition that is quite common in such drives.
With the time slice synchronization described above with reference to FIG. 1, the charge exchange currents of all drives in a servo system, which operate near a rotation speed of zero, are synchronized. In the worst case, the maximum interference current in the system is identical to the sum of the interference currents of the individual drives.
Conventionally, this problem is addressed by designing the line filter for the worst case scenario.
It would therefore be desirable and advantageous to overcome the fundamental problem of asymmetric interference currents in a group of electric drives, without impairing the synchronization of these drives.